|
Check out my updated resume [pdf] or
[text]
I'm a 2nd year Master's student in the Department of Electrical
and Computer Engineering at Virginia Tech.
I work with Professor Michael Hsiao
in Verification and Testing.
Formal Verification and Testing of VLSI Systems. My research focuses on Hybrid techniques consisting of applications of BDD, SAT, ATPG, Coverage.
Virginia Tech, Blacksburg, VA
Master of Science (ongoing), Computer Engineering
Advisor: Professor Michael Hsiao
IIT Kharagpur, Kharagpur, India
B.Tech. in Computer Science and Engineering (May 2004)
Synopsys (India) Pvt. Ltd., Bangalore, India
I was working in Synopsys, Bangalore from July, 2004 to July 2006 before I came to Virginia Tech.
I was R&D Engineer II in the Verification Group. My work there involved the development of Functional Coverage (also called Testbench Coverage)
technology in SVTB (System Verilog TestBench), and NTB (Native TestBench for OpenVera).
Qualcomm Inc., San Diego
I was an Engineering Intern in the Verification Group of Qualcomm Inc., San Diego from May, 2007 to July 2007.
My work there involved the development of the Testbench especially the Constraints and the Functional Coverage part of it for some of the Blocks of the Design.
I also got to work with the Synopsys Engineers for the setup of a new technology in the Simulation based Coverage Domain in Qualcomm's Verification Environment.
Anupam Shrivastava
Email: anupams (at) vt.edu
Ph: 540-808-5010, (540) 231-8848 (W),
Fax:
Home Address
4800 K, 1253, Progress St NW,
Blacksburg, VA - 24060.
Office Mail Address
350, Whittemore Hall,
The Bradley Dept. of Electrical and Computer Engineering,
Virginia Tech (0111),
Blacksburg, VA - 24061.
Hit Counter
|
