ECE 5530 Homework 11

By Andrew Love

Problem Description:

We wish to do three different modifications to a bitstream using JBits. Part 1 involves inverting the output result, part 2 involves switching wires around, and part 3 involves rerouting wires to a new CLB and then sending this new value into the registers instead of the old value. We will be using Vertex 2 FPGAs to run the hardware and JBits and ADB will be used to do the bitstream conversion through java.

Solution Description:

For this project, I first needed to write the core VHDL program that I would be modifying throughout the course of the project. The function that was implemented was simple:

0001 input => 0001 output

0010 input => 0010 output

0100 input => 0100 output

1000 input => 1000 output

other input => 0000 output

The output was also to be stored in registers in slice 4,4. Since each slice can only has two 1-bit registers, the second slice 4,5 was also used. Both of these slices occur in CLB 2,2. To implement the registers properly, I needed to create a component and then have VHDL place it in the design. REG4.vhd is the 4-bit register component. Another component was instantiated to implement the control logic, control_logic.vhd. This is not necessary for the current implementation, but if we wanted to put the control logic in a specific portion of the chip, this instantiation would let us do it.

Addresses:

0x800000 – Sanity check register. Can write to it, then read back that number to make certain the board is operational.

0x801000 – writing to this sets the input to the design and reading from it gets the output of the design.

The .vhd and additional project files necessary to create the basic VHDL design are located here:

http://filebox.vt.edu/users/arl8c/public/ECE5530/HW11/VHDL/

The fpga_a.bit file does not have the signbit added to it yet, so that JBits can be run to edit it. The first script only goes through a few combinations, including 1,2,4,8 and some others to check the design for parts 1 and 2. The second script goes through all the numbers from 1-15 to check the performance in part 3.

Part 1:

The first part requires that the control logic in the LUTs be modified to fit the following design:

0001 input => 1110 output

0010 input => 1101 output

0100 input => 1011 output

1000 input => 0111 output

other input => 1111 output

This is merely an inversion of what the initial control logic did to the data. First, the control logic was found to be placed in the LUTs in CLB 2,2 as inputs to the registers placed in that location. In order to modify these LUTs, the control data from those LUTs was read into JBits, inverted, and then placed back into the bitstream. The code to implement that and a .bit file which can be run to do so both appear in the following location:

http://filebox.vt.edu/users/arl8c/public/ECE5530/HW11/Part_1/

Note that the data is located in the F and G LUTs of slices 0 and 1. This corresponds to slices 4,4 and 4,5 according to VHDL notation. The syntax to run this program is: WriteLUTs_mod -<device> <infile.bit> <outfile.bit>

Part 2:

The second part requires that the wires that connect the lower two bits of the output register be switched with one another. Therefore, a proper design will have the following structure:

0001 input => 0010 output

0010 input => 0001 output

0100 input => 0100 output

1000 input => 1000 output

other input => 0000 output

This modification is done to the original bitstream. In order to implement this design, the lower two registers needed to be identified. They were found to reside in slice 1 of CLB 2,2. Once this is done, the output to those registers is known. These outputs are connected through a series of wires to another location, where they will then be outputted to the console. This location is unknown. Therefore, ADB is used to trace the route from the register outputs to their sinks. The resulting linked lists can be traversed and the name of the sink can be found. Once this is done, the old routes need to be removed. A simple ADB unrouting command will do this. The net now has no connection between the old inputs and the new ones. Therefore, a new route can be created from each of the inputs to the sink of the other. This is done through the ADB router. The java code which implements this as well as the .bit file that can be run to do so appears in the following location:

http://filebox.vt.edu/users/arl8c/public/ECE5530/HW11/Part_2/

Part 3:

The last part required that new logic be created in a different CLB and that the inputs to the original CLB be rerouted to this location. The output from this new CLB would then be routed back into the LSB register of the original CLB, avoiding the control logic for this CLB entirely. The new logic outputs a 1 when the inputted number is prime and a 0 otherwise. Therefore, 1s are outputted for the following numbers:

1, 2, 3, 5, 7, 11, 13

Zero was considered to not be prime for the purposes of this design.

One important note to make is that the array that is inputted into the LUT is actually the inversion of the expected array. For example, one would think that the representation of the array would be the following (Starting from 0 and counting up to 15):

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 1 1 1 0 1 0 1 0 0 0 1 0 1 0 0

Instead, the array must be inverted prior to inserting it into the LUT.

Another key feature is that the inputs to the original LUT are not necessarily in the intuitive msb to lsb order. Instead, they are shuffled around. A careful look at the design revealed that the following is the ordering:

Assumed ordering: f4 f3 f2 f1

Actual ordering: f3 f4 f1 f2

Therefore the array needed to be changed to look like the following:

Ideal ordering: 0 1 1 1 0 1 0 1 0 0 0 1 0 1 0 0

Adjusted ordering: 0 1 1 1 0 0 0 1 0 0 1 1 0 0 1 0

Another solution would have been to switch the wiring around during routing.

Now that the new control logic is placed properly in the correct location, significant routing and unrouting needs to occur. The inputs to the original CLB are traced to their source, unrouted, and then routed to the new CLB. The output of the new CLB is then routed to an input to the old CLB. In the following figure, the new control logic CLB’s output is routed into the BY1 input of the original CLB. The other thing to change in the original CLB is the mux located right before the G register input (Y1 mux CLB_BY_S1 à YQ_D_S1). The name of this mux is DYMUX. The mux originally connects the G register to the GLUT and now it is changed to connect to the BY1 input.

The java code which implements this as well as the .bit file that can be run to do so appears in the following location:

http://filebox.vt.edu/users/arl8c/public/ECE5530/HW11/Part_3/

These programs are so simple that they all run at 100 MHz.