Title: Design Engineer
Organization: Freescale Semiconductors, India.
Duration: Jul'03 - Jun'06

1. Module level Verification.
2. Full-chip Integration.
3. Constraint based Random Verification.
4. BIST - principles and mechanisms.

Title: Graduate Intern Technical
Organization: Intel, Santa Clara, USA.
Duration: May'07 - Aug'07

1. Enhancing ATPG algorithm for faster fault detection using learning techniques.

Technical Skills

Language	Tools
Hardware Description Language	Verilog
Verification Language	Synopsys Vera
Software Language	C, C++
Operating Systems	Windows-98, UNIX, Solaris, Linux
Scripting Language	Perl
Others	Matlab