ASIP with customized instructions is another approach to implement Virtual Secure Circuit (see below for definition). Unlike the dual-core PowerPC system, the ASIP-based approach aims to emulate the dual-rail pre-charge circuit with only one single processor. To fulfill this purpose, half of a processor needs to behave as the direct-rail while the other half as the complementary-rail. Such processor is called 'balanced processor'. We designed a balanced processor by customizing a Leon3 processor. In detail, we added two simple customized instructions, including balanced AND (b_and) and balanced OR (b_or). Together with the balanced programming method based on the bitslicing programming, we have been able to implement the full AES in the protected VSC fashion. With Measurement to Disclosure (MTD) as the quantification approach, the custom-instruction VSC offers 20 times more security.

We present a concept, called Virtual Secure Circuit (VSC), to enable the processors to emulate the dual-rail pre-charge circuits with software programming. The objective is to protect the software cryptography against Side-Channel Attacks. VSC on the dual-core PowerPC system is an implementation of this concept, where each PowerPC core is programmed to have the same behavior of one rail of the dual-rail circuit. With 3 techniques, including 1) programming with complimentary instruction pairs, 2) inserting pre-charge instructions, and 3) synchronizing two PPC cores cycle by cycle, we successfully ported the dual-rail pre-charge technique to dual-core software. Experimental results showed that the security of the VSC-based software had been improved by 80 times, which is comparable to the dual-rial pre-charge circuit (e.g. WDDL). Besides the security improvement, another good feature is that our design does not need any modification to the processors. Details can be found in a technical report [pdf]. The design files for the SASEBO-G platform are available upon requests.