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06/17/2011 I successfully defended my Ph.D. dissertation: SCA-Resistant and High-Performance Embedded Cryptography Using Instruction Set Extensions and Multi-Core Processors.

 

03/19/2011 I attended Design, Automation and Test in Europe (DATE2011) in Grenoble, France. Our work on performance analysis of SHA-3 candidates was presented on Mar. 17.

 

10/30/2010

 From Oct. 24 to Oct. 27, I enjoyed my stay in Scottsdale, AZ. Two papers written by me and my colleagues were presented in Workshop on Embedded Systems Security (WESS'2010) , and Embedded System Week (ESWEEK'2010) respectively.

 

6/7/2010

 From Jun. 7 to Jun. 11, I attended Trusted Infrastructure Workshop (TIW) 2010 , hold by CyLab, Carnegie Mellon University. The workshop talked about different aspects of Trusted Computing. It's a wonderful week in Pittsburgh.

 

5/3/2010

 I sccessfully passed my Prelim Exam on 4/28/2010. So I have been upgraded to a Ph.D. candidate, looking forward to graduation in one year.

 

3/8/2010

 I am attending Design, Automation and Test in Europe (DATE2010) conference in Dresden, Germany. Three presentations will be given by me.
1) "pSHS: A Scalable Parallel Software Implementation of Montgomery Multiplication for Multicore Systems". This talk discusses my research on high-performance public-key cryptography on multicore systems. Place: Room - Konferenz 2; time: 14:30-15:00, 3/10/2010.
2) "A method to reduce side-channel leakage for masked circuits" at the EDAA/ACM PhD forum. I will be showing part of my PhD work on secure circuits against side-channel analysis. Place: Room - Terrace; time: 19:00 - 21:00, 3/8/2010.
3) "Reversible Logic Synthesis through Ant Colony Optimization". This is a work on reversible logic synthesis published by Min Li, et. al. I will do the presentation for the authors in the IP session. Place: Room - Konferenz 1; time: 14:30-16:00, 3/09/2010.

 

3/6/2010

 I visited IAIK institute in Graz University of Technology, Austria, for 2 days. It was a pleasure to discuss with researchers in the same area - side-channel attack.

 

2/23/2010

 I attended International Symposium on FPGAs (FPGA2010) in Monterey, CA. The presentation was made on "Combining Multicore and Reconfigurable Instruction Set Extensions". This is a my work in Microsoft Research (MSR) during the last summer. Here, I want to thank the Embedded System group in MSR for the great oppotunity for learning this interesting area.

 

7/27/2009

 I attended IEEE International Workshop on Hardware-Oriented Security and Trust (HOST09) in San Francisco and gave a presentation on 'Early feedback on Side Channel Risks with Accelerated Toggle Counting'. It is my pleasure to have this chance to discuss this topic with other researchers. I am also glad to meet some new friends.

 

5/23/2009

 I am doing my internship in Microsoft Research. For the entire summer, I am going to build a multi-core system with MIPS processors. The critical problem is how to realize the on-chip and on-board interprocessor communication with high throughput, low latency and convenience for parallel programming.