Publications
| Z. Chen, A. Sinha, and P. Schaumont, "Using Virtual Secure Circuit to Protect Embedded Software from Side Channel Attacks ," IEEE Transactions on Computers, (accepted). |
| Z. Chen and P. Schaumont, "A Parallel Implementation of Montgomery
Multiplication on Multi-core Systems: Algorithm, Analysis, and Prototype," IEEE Transactions on Computers, vol. 60, no. 12, Dec. 2011, pp. 1692-1703. [pdf] |
| Z. Chen, X. Guo, A. Sinha, and P. Schaumont, "Data-Oriented Performance Analysis of SHA-3 Candidates on FPGA Accelerated Computers," Design, Automation and Test in Europe (DATE2011). |
| A. Sinha, Z. Chen and P. Schaumont, "A Comprehensive Analysis of Performance and Side-Channel-Leakage of AES SBOX Implementations in Embedded Software," Workshop on Embedded Systems Security (WESS2010), 2010. [pdf] |
| Z. Chen, A. Sinha and P. Schaumont, "Implementing Virtual Secure Circuit Using A Custom-Instruction Approach," International Conference on Compilers Architecture and Synthesis for Embedded Systems (CASES 2010). [pdf] |
| Z. Chen, and P. Schaumont, "Virtual Secure Circuit: Porting Dual-Rail Pre-charge Technique into Software on Multicore," IACR ePrint Archive 2010/272, April 2010. [pdf] |
| Z. Chen, and P. Schaumont, "pSHS: A Scalable Parallel Software Implementation of Montgomery Multiplication for Multicore Systems," Design, Automation and Test in Europe (DATE2010), pp. 843-848, 2010. [pdf] |
| Z. Chen, R. N. Pittman, A. Forin, "Combining Multi-core and Reconfigurable instruction Set Extensions," ACM SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA2010), pp. 33-36, 2010. [pdf]. |
| Z. Chen, R. N. Pittman, A. Forin, "MultiCore eMIPS," Microsoft Research Technical Report MSR-TR-2009-113, 2009. [pdf]. |
| Z. Chen, and P. Schaumont, "Early Feedback on Side-Channel Risks and Accelerated Toggle Counting," IEEE International Workshop on Hardware-Oriented Security and Trust (HOST2009), pp 90-95, 2009. [pdf] |
| Z. Chen, S. Haider, and P. Schaumont, "Side-Channel Leakage in Masked Circuits Caused by Higher-Order Circuit Effects," International Conference on Information Security and Assurance (ISA2009) , pp 327-336, 2009. [pdf] |
| Z. Chen, R. Nagesh, A. Reddy, and P. Schaumont, "Increasing the Sensitivity of On-Chip Digital Thermal Sensors with Pre-Filtering," IEEE Computer Society Annual Symposium on VLSI (ISVLSI2009), 2009. [pdf] |
| Z. Chen, X. Guo, R. Nagesh, A. Reddy, M. Gora, and A. Maiti, "Hardware Trojan Designs on BASYS FPGA Board," Embedded System Challenge Contest in Cyber Security Awareness Week (CSAW2008), 2008. [pdf] |
| Z. Chen, S. Morozov, and P. Schaumont, "A Hardware Interface for Hashing Algorithm," ePrint IACR Archive, 2008/529, 2008. [pdf] |
| Z. Chen, and P. Schaumont, "Improving Secure Hardware Masking Using an Equalization Technique," Workshop on Embedded Systems Security (WESS2008), 2008. [pdf] |
| Z. Chen, and P. Schaumont, "Slicing Up a Perfect Hardware Masking Scheme," Workshop on Hardware-Oriented Security and Trust(HOST2008), 2008. (also a poster in Design Automation Conference DAC 2008) [pdf] [pdf] |
| X. Guo, Z. Chen, and P. Schaumont, "Energy and Performance Evaluation of an FPGA-based SoC Platform with AES and PRESENT Coprocessors," Workshop on Systems, Architectures, Modeling, and Simulation 2008. [pdf] |
| Z. Chen, and Y. Zhou, "Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side-Channel Leakage," Workshop on Cryptographic Hardware and Embedded System (CHES2006), 2006. [pdf] |
Posters
| K. Mukunda, Z. Chen, and P. Schaumont, "Comparing Embedded Multicore & General Purpose Multicore for Data-Level Parallel Programming," 1st "CESCA DAY" workshop, May, 2010, Virginia Tech. |
| A. Sinha, Z. Chen, and P. Schaumont, "Protecting Embedded Cryptography Using Custom-Instruction Based Virtual Secure Circuits," 1st "CESCA DAY" workshop, May, 2010, Virginia Tech. |
| Z. Chen, "A method to reduce side-channel leakage for masked circuits," EDAA/ACM DATE2010 PhD forum, 2010, Dresden, Germany. |
| Z. Chen, R. N. Pittman, and A. Sandro, "Multi-Core eMIPS," Microsoft Research Faculty Summit, 2009, Redmond, WA. |
| Z. Chen, and P. Schaumont, "Slicing Up a Perfect Hardware Masking Scheme," SIGDA/DAC University Booth 2008; [pdf] |
| Z. Chen, X. Guo, R. Nagesh, A. Reddy, M. Gora, and A. Maiti, "Hardware Trojan Designs on BASYS FPGA Board," Embedded System Challenge Contest in Cyber Security Awareness Week (CSAW2008), 2008. [pdf] |
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