My research focuses on High-Performance Implementation of Trustworthy Cryptographic . I am currently working on 1) secure embedded processor design and programming against side-channel attacks, including multi-core architectures and ASIPs with specialized instruction sets; and 2) high-performance cryptography on high-end FPGA accelerated computers.

During my previous research, I have been working on the following topics: 1) ASIC designs for both high-performance and area-efficient cryptography, 2) parallel software programming for public-key algorithms based on multicore systems, and 3) Design Flow for Secure Hardware/software Codesign.

Side-channel attacks present a great concern to implementations of cryptography on embedded systems. Our in-lab attacks show that 128-bit AES cryptography can be broken within minutes. In comparison, it takes brute-force attacks centuries to finish the same task even with the current most powerful super-computers.

This research aims to protect the most popular embedded implementations of cryptography, software, from different categories of side-channal attacks. Our approach stands at the processor-architecture level and provides the protection which is transparent to software programmers. By now, we already proposed two secure embedded processor solutions, including the dual-core complementary processor and the specialized instruction set complementary processor. The corresponding programming methods for the secure processors can be automated and integrated into tools. Experimental results show that our architecture-level solutions provide similar secure protection as circuit-level solutions. Since our solutions serve software, it is more flexible and can be more broadly used.

We have seen a number of computing platforms equiped with FPGA accelerators, but the general-purpose computer platform was usually not one of them. Recently, due to the difficulties on increasing a single core's performance and on accelerating a single application with multicore, computer engineers start considering to insert FPGAs into the general-purpose computers as a new option to reduce the latency of every single program. The in-socket FPGA accelerated system designed by Nallatech Inc. follows the above concept which integrates an Intel quad-core Xeon processor and a Xilinx Virtex-5 FPGA into symmetric sockets connected by the front-side bus.

This research investigates the new computer system to accelerate cryptographic applications. By now we have found a hw/sw codesign solution that accelerates Hash applications 10 times faster than software-only solutions. We will continue working in this direction and reporting more exciting results.