Eric Xu Guo

PhD student
365 Durham Hall
Virginia Tech
Blacksburg, VA, 24061
USA


Email: xuguo@vt.edu
About me

I came to Bradley Department of ECE, Virginia Tech in August, 2007. Now, I am a PhD candidate in the Secure Embedded Systems (SES) Group with Dr. Patrick Schaumont as my PhD advisor.

Research

 

 
  • HW/SW Co-design for secure embedded systems.
  • Applied cryptography.
  • FPGA-based SoC design.
  • Low power digital circuit design.
Education
  • Ph.D. student, Electrical & Computer Engineering, Virginia Tech, Fall 2007-present.
  • M.S., Electronic Science and Technology(digital VLSI design), Huazhong Univ. of Sci. & Tech., Wuhan, China, Fall 2004-Spring 2007. Thesis title: Research and Design of Image Backend Processing Module Applied to LCD Scalar.
  • B.S., Electronic Science and Technology, Huazhong Univ. of Sci. & Tech., Wuhan, China, Fall 2000-Fall 2004.
News
05/18/2009: From May 18 to Aug. 22, 2009, I will work at University of Southern California - Information Sciences Institute as a Visiting Research Assistant. My primary task will be implementing, verifying, and evaluating hardware kernels to run as part of the runtime application based on differnent FPGA platforms and design flows.
 
05/01/2009: I come back from two weeks' travel in Europe. During the stay, I gave a long presentation at DATE09 conference in Nice, France, and performed a short academic visit to COSIC/ESAT group at K.U.Leuven, Belgium.
Current Pojects

 
8/2009~Present

SHA - FPGA : Methodology for Benchmarking of Hardware Implementation of NIST SHA-3 Competition Candidates

Standard Hash Hardware Interface by Secure Embedded System (SES) group at Virginia Tech

SHA-3 Competition 2nd Round Candidates by NIST

10/2008~Present

SCAR & FT - ECC : Side-Channel Attack Resistant and Fault Tolerant Elliptic Curve Cryptography System Design

Elliptic Curve Scalar Multiplication: Attacks vs. Countermeasures by collaboration between Secure Embedded System (SES) group at Virginia Tech and ESAT-COSIC at K.U.Leuven

Presentation Slides for CHES09 Conference

Publications
  
[PDF]
X. Guo, J. Fan, P. Schaumont, and I. Verbauwhede, "Programmable and Parallel ECC Coprocessor Architecture: Tradeoffs between Area, Speed and Security", Workshop on Cryptographic Hardware and Embedded Systems (CHES 2009), LNCS5747, pp. 289-303, Sep. 2009.
[PDF]
X. Guo, P. Schaumont, "Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA based SoC Platform", 5th International Workshop on Applied Reconfigurable Computing (ARC2009), LNCS5453, pp. 169-180, Springer Verlag, Feb. 2009.
[PDF]
X. Guo, P. Schaumont, "Optimizing the HW/SW Boundary of an ECC SoC Design Using Control Hierarchy and Distributed Storage", Design, Automation and Test in Europe (DATE2009), Apr. 2009.
[PDF]
Z. Chen, X. Guo, R. Nagesh, A. Reddy, M. Gora, and A. Maiti, "Hardware Trojan Designs on BASYS FPGA Board", Embedded System Challenge Contest in Cyber Security Awareness Week (CSAW08) (Technical Report), 2008. (4th Place with Honorable Mention)
[PDF]

X. Guo, Z. Chen, and P. Schaumont, "Energy and Performance Evaluation of an FPGA-based SoC Platform with AES and PRESENT Coprocessors", International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2008), LNCS5114, pp. 16-115, Springer Verlag, Jul. 2008.
[PDF]
J. Xing, X. Zou, X. Guo, "Ultra-Low Power S-Boxes Architecture for AES", The Journal of China University of Posts and Telecommunications, Vol.15, no.1, Mar. 2008
[PDF]
Z. Liu, X. Guo, Y. Chen, Y. Han and X. Zou, "On the Ability of AES SBoxes to Secure Against Correlation Power Analysis", in Proceedings of 3rd Information Security Practice and Experience Conference (ISPEC 2007), LNCS 4464,  pp. 43-50, Springer Verlag, 2007.
[PDF]

J. Xiao, X. Zou, Z. Liu, X. Guo, "A Novel Adaptive Interpolation Algorithm for Image Resizing", International Journal of Innovative Computing, Information and Control, vol.3, no.6(A), pp. 1335-1345, 2007.
[PDF]

X. Guo, Z. Liu, J. Xing, W. Fan and X. Zou, "Optimized AES Crypto Design for Wireless Sensor Networks with a Balanced S-box Architecture", in Proceedings of International Conference on Informatics and Control Technologies (ICT2006), pp. 203-208, IET, 2006. (Merit Paper Award)

[PDF]

J. Xiao, X. Zou, Z. Liu, X. Guo, "Adaptive Interpolation Algorithm for Real-time Image Resizing", in Proceedings of International Conference on Innovative Computing, Information and Control (ICICIC'06), vol. 2, pp. 221-224, IEEE, 2006.
Posters
  
[PDF]
 Z. Chen, X. Guo, R. Nagesh, A. Reddy, M. Gora, and A. Maiti, "Hardware Trojan Designs on BASYS FPGA Board", Embedded System Challenge Contest in Cyber Security Awareness Week (CSAW08), 2008. (4th Place with Honorable Mention)
Presentations
  
[PPT]
"Optimizing the HW/SW Boundary of a Runtime Programmable and Parallel ECC Coprocessor Design Using Control Hierarchy and Distributed Storage", ESAT-COSIC, K.U.Leuven, Belgium, April 2009.
   
Useful Links
 
 

VLSI Related Conferences and Workshops (CFP)

Upcoming and Recent FPGA/VLSI/CAD Conferences (CFP)

List of VLSI / IC Conferences and Workshops (CFP)

Cryptography Conferences (CFP)

 
   

Copyright: These materials are presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights are retained by authors or by other copyright holders.

Last updated on: Sep. 28, 2009
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