Dr. Xu "Eric" Guo [CV]

PhD, Computer Engineering
469 Durham Hall
Virginia Tech
Blacksburg, VA, 24061


Note: After graduation from SES@VT in May 2012, I find a new home for my website:


Current Projects
Previous Projects
Useful Links
About me

I joined Bradley Department of ECE, Virginia Tech in fall, 2007. From August 2007 to May 2012, I was a Graduate Reseaerch Assistant at Secure Embedded Systems (SES) Lab in the Center for Embedded Systems for Critical Applications (CESCA) with Prof. Patrick Schaumont as my PhD advisor. I earned a doctoral degree in Computer Engineering from Virginia Tech in May 2012.

  • HW/SW Co-design for Secure Embedded Systems
  • Secure Hardware Design for FPGAs and ASICs
  • System-on-Chip Integration of Cryptographic Coprocessors
  • Side-Channel Attacks on Cryptographic Hardware
  • Fault Attacks on Elliptic Curve Cryptography
  • Performance Evaluation of Cryptographic Hardware and Software




(My research key words cloud by wordle based on my publication titles)


Virginia Polytechnic Institute and State University

  • Doctor of Philosophy in Computer Engineering, May 2012
  • Dissertation: "Secure and Efficient Implementations of Cryptographic Primitives"
  • Advisor: Prof. Patrick Schaumont

Huazhong University of Science and Technology, China

  • Master of Science in Electronic Science and Technology, April 2007.
  • Dissertation: "Research and Design of Image Backend Processing Module Applied to LCD Scalar"
  • Advisor: Prof. Zhenglin Liu
  • Bachelor of Science in Electronic Science and Technology, July 2004.
01/05/2012: I successfully defended my PhD dissertation: "Secure and Efficient Implementations of Cryptographic Primitives".
18/03/2012: I attended the DATE'12 conferernce in Dresden, Germany, and gave a presentation in the session of "Architecture and Building Blocks for Secure Systems" about our SHA-3 ASIC.
02/28/2012: Our invited paper, titled "Design and Benchmarking of an ASIC with Five SHA-3 Finalist Candidates", got accepted in a special issue of Microprocessors and Microsystems: Embedded Hardware Design (MICPRO) on "Digital System Security and Safety"!
11/16/2011: Two submissions related to SHA-3 have been accepted by LC2011, Louvain-la-Neuve, Belgium and DATE2012, Dresden, Germany.
09/27/2011: The VT SHA-3 chip was announced at CHES2011 Rump Session in Nara, Japan. The demo of SHA-3 chip running on SASEBO-R board was shown in the CHES2011 Exhibition.
08/17/2011: The VT SHA-3 chip has been fabricated, packaged and fully tested. It contains a total of five SHA-3 finalists with Round 3 specifications (updated in Jan., 2011) and a reference SHA256. Free sample chips are now available upon request. Please see more information here.
06/11/2011: I attended the DAC 2011 Work-In-Progress (WIP) poster session in San Diego, CA, and annouced our SHA-3 ASIC with first silicon sucess to the whole DAC community.
02/15/2011: Our SHA-3 ASIC chip has been sent out to IBM MOSIS for tape-out with 130nm standard-cell technology. It is highly possible that it will be the first SHA-3 ASIC chip implementing all the SHA-3 five finalists with the latest Round 3 specifications.
01/19/2011: I came back from a SHA3 ASIC design review with VLSI Design/Automation Lab at Univ. of Michigan. It's my great pleasure to meet with Dr. Blaauw and his students.
11/19/2010: Check our new VT-SHA3 website with all the opensourced RTL codes, simulation files, and FPGA/ASIC scripts!
10/24/2010: I attended the ECC2010 workshop at Microsoft Research in Redmond, Washington, USA. Meet many world-class researchers there to celebrate the 25th aniversary of ECC.
09/24/2010: I gave a seminar to all CESCA faculties and students discussing the hardware benchmarking issues of NIST SHA-3 2nd Round Competition candidates. You can access the presentation slides following this Link.
08/27/2010: I came back from the trip to NIST The 2nd SHA-3 candidate conference at Santa Barbara, CA. All the presentation slides and papers can be found at this Link.
06/16/2010: I had a very nice trip to Anaheim, CA to attend HOST'10 conference (co-located with DAC'10). I gave a joint tutorial presentation with E. De Mulder from K.U.Leuven titled, "State-of-the-art of secure ECC implementations: a survey on known side-channel attacks and countermeasures". I also had a co-authored poster at HOST'10 about SHA-3. Besides, I also enjoyed a wonderful 1-day travel to Hollywood and Los Angeles.
05/06/2010: I was honored to become a panelist in the student panael session at "CESCA Day", and I also had a poster in the afternoon poster session II. There were a lot of helpful discussion and fun in this great one day event. (Virginia Tech's Center for Embedded Systems for Critical Applications (CESCA) will be holding its annual workshop titled "CESCA Day" )
04/10/2010: Just came back from a two days NIST meeting at George Mason Unversity about a NIST ARRA sponsered project, entitled "Environment for Fair and Comprehensive Performance Evaluation of Cryptographic Hardware and Software", which is a joint work with GMU, VT and UIC. During the meeting, I gave a short talk and presentd a demo for the SHA-3 ASIC prototying on SASEBO-GII and practical power measurement of SHA-3 FPGA implementations.
05/18/2009: From May 18 to Aug. 22, 2009, I will work at University of Southern California - Information Sciences Institute as a Visiting Research Assistant. My primary task will be implementing, verifying, and evaluating hardware kernels to run as part of the runtime application based on differnent FPGA platforms and design flows.
05/01/2009: I come back from two weeks' travel in Europe. During the stay, I gave a long presentation at DATE09 conference in Nice, France, and performed a short academic visit to COSIC/ESAT group at K.U.Leuven, Belgium.

2012 awarded by the Travel Fund Program of GSA, Virginia Tech.
2010 awarded a stipend funded under NSF grant CCF-1057551 to attend ECC2010 workshop at Redmond, WA.
2009 funded by the Pratt funds to visit ESAT/COSIC, K.U.Leuven, Belgium.
2008 awarded by the Travel Fund Program of GSA, Virginia Tech.
2008 4th Place with Honorable Mention, Embedded System Challenge in Cyber Security Awareness Week (CSAW08) - National Hardware Trojan Design Contest, USA.
2006 Outstanding Graduate Pace-setter, awarded by Graduate School, HUST. (10/19,000)
2006 Merit Paper Award, Int. Conf. on Informatics & Control Technologies (ICT06).
2006 Full Fellowship, Graduate School, HUST.
2006 Excellent Research Paper scholarship, Graduate School, HUST. (2/137)
2005 Outstanding Teamwork Award, 'Altera Cup' China 5th Graduate EDA Contest.
2005 Excellent Student Leader Scholarship, Graduate School, HUST. (6/137)
2004 Excellent Researcher Scholarship, Graduate School, HUST. (6/137)
2004 Best Presentation Award, Annual Academic Conference of EST Department, HUST.

Membership & Services


IEEE Student Member since 2006;
ACM Student Member since 2010.


Reviewer for Journals:

IEEE Transactions on Computers (IEEE-TC)
IEEE Transactions on VLSI (IEEE-TVLSI)
IEEE Embedded Systems Letters (IEEE-ESL)
IEEE Transactions on Circuits and Systems I (IEEE-TCAS-I)
ACM Transactions on Embedded Computing Systems (ACM-TECS)
ACM Transactions on Reconfigurable Technology and Systems (ACM-TRETS)
Elsevier Integration the VLSI Journal
Springer Transactions on Computational Science (Springer-TCS)
ACTA International Journal of Computers and Applications
Springer Journal of Cryptographic Engineering


Reviewer for Conferences:


Current Projects
Previous Projects
Useful Links

Last updated on: May 8, 2012
since Feb. 11, 2008