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Dr. Xu "Eric" Guo [CV]

PhD, Computer Engineering
469 Durham Hall
Virginia Tech
Blacksburg, VA, 24061
USA

Email: xuguo@vt.edu

Note: After graduation from SES@VT in May 2012, I find a new home for my website: https://sites.google.com/site/url2ericguo
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11/2011~05/2012

Lightweight Hash: The Technology Dependence of Cost Analysis of Lightweight Hash Designs

Descriptions: Cryptographic algorithm and protocols need to be tailored for implementation in many constrained environments, including RFID tags, wireless sensors, smart cards, and mobile devices. Lightweight Cryptography is a generic term that captures new efforts in this area, covering lightweight cryptography proposals as well as lightweight implementation techniques. This work demonstrates the influence of technology selection when comparing different lightweight hash designs and when using lightweight cryptography techniques to implement a hash design. First, we demonstrate the impact of technology selection to the cost analysis of existing lightweight hash designs through two case studies: the new lightweight proposal Quark and a lightweight implementation of CubeHash. Second, by observing the interaction of hash algorithm design, architecture design, and technology mapping, we propose a methodology for lightweight hash implementation and apply it to Cubehash optimizations. Finally, we introduce a cost model for analyzing the hardware cost of lightweight hash implementations.

9/2011~05/2012

SCA-SHA3: Side-Channel Analysis (SCA) Evaulation of NIST SHA-3 Hardware Implementations

Descriptions: The five SHA-3 finalists have been implemented in both hardware and software on different platforms. So far, we have mainly looked at the performance benchmarking in comparing different candidates. We think once the SHA-3 candidates are implemented they will also become the targets of several advanced implementation attacks, such as Side-Channel Analysis (SCA) attacks and Fault Injection attacks. Based on the power measurements of our developed SHA-3 ASIC, we can already observe different power patterns as shown in the power traces above. It would be very meaningful to investigate whether by using the Power Analysis based attacks (the basic methodology is shown in the figure above) we can explore the SCA vulnerabilities of the SHA-3 algorithms and try to give some light on how to design the SHA-3 in a more secure fashion.

11/2010~05/2012

SHA3-ASIC: Chip Tape-out of NIST SHA3 Third Round Five Finalists Using IBM MOSIS 130nm Technology

Descriptions: From the "NIST Status Report on the Second Round of the SHA-3 Cryptographic Hash Algorithm Competition", we have already seen that NIST considered the hardware performance results as an important factor during the Third Round candidates selection process.

The SHA-3 chip we have already delivered to IBM MOSIS for tape-out reflects the latest tweaks for all the five SHA-3 Finalists, which have been listed in the NIST SHA-3 Competition Official Website. It is highly possible that this chip will be the first SHA-3 chip containing all the five SHA-3 finalists. We hope the following analysis and measurements based on our SHA-3 chip tape-out can provide more insights to NIST in the SHA-3 hardware evaluation, and finally help NIST to select the winner of the SHA-3 competition at the beginning of 2012.

The VT SHA-3 chip is now FREE available upon request. Please check here for more information.

Related Links:

VT-SHA3 Project Website by Secure by Secure Embedded System (SES) group at Virginia Tech

Standard Hash Hardware Interface by Secure Embedded System (SES) group at Virginia Tech

SHA-3 Competition 3nd Round Candidates by NIST

SASEBO-R Board (Target Chip Testing Platform) by AIST (the National Institute of Advanced Industrial Science and Technology), Japan

9/2010~05/2012

High Performance Cryptographic Computing: System-Level Design and Analysis for Cryptography on FPGA Accelerated Computers

Descriptions: As for a case study, we have tried to map three SHA-3 candidates, CubeHash, Keccak and SIMD on a FPGA accelerated computer. We noticed that all these crypto-benchmarking proposals pay little or no attention to the system integration effects of a hash primitive. For example, they optimistically assume that the messages originate from a high-bandwidth data source. They also assume a random-access storage architecture that provides fast access to the messages regardless of their length.

However, real computers have severa limits, such as slow disks, limited cache memories, and computer busses with limited bandwidth. Moreover, exploiting parallelism in a computer architecture is complex, even for a simple task such as hashing multiple messages in parallel. We demonstrate that, on real computer architectures, there is a highly non-linear dependence of computer performance on the major hash application parameters (message size, message multiplicity, and hash candidate). This dependence has so far not been covered by crypto-benchmarks.

Related Links:

Intel QuickAssist Technology supports the FSB-FPGA Accelerator

Intel Xeon FSB FPGA Socket Fillers by Nallatech Company

 

8/2009~05/2012

SHA - FPGA to SHA - ASIC: Methodology for Benchmarking of Hardware Implementation of NIST SHA-3 Competition Candidates

Descriptions: For the second phase of the competition, NIST is looking for additional cryptanalytic results, as well as for performance evaluation data on hardware platforms. The SHA-3 submissions were made as a software reference implementation in combination with a set of test vectors. This pragmatic approach leverages ubiquitous computer infrastructure as a standard evaluation platform, and it suits the purpose of cryptanalysis. However, the reference implementations in C are also far away from actual hardware design. As a result, significant additional design work is required before the SHA-3 candidates can be evaluated in terms of hardware cost.

In contrast to software implementations, which can be characterized based on performance (execution time) only, hardware implementations have at least one additional dimension: resource cost, in addition to performance. Indeed, for hardware implementations, the architecture of the design represents an additional degree of design freedom. As a result, there is no single optimal hardware implementation. Every design has to be considered as a combination of performance under a given resource cost. This aspect complicates the comparison of designs, because one may look for minimal resource cost under a given performance, or else for maximal performance under a given resource cost. Hence, a hardware benchmarking methodology needs to take this duality into account.

Related Links:

VT-SHA3 Project Website by Secure by Secure Embedded System (SES) group at Virginia Tech

Standard Hash Hardware Interface by Secure Embedded System (SES) group at Virginia Tech

SHA-3 Competition 2nd Round Candidates by NIST

SASEBOII Board by AIST (the National Institute of Advanced Industrial Science and Technology), Japan

10/2008~05/2012

SCAR & FT - ECC : Side-Channel Attack Resistant and Fault Tolerant Elliptic Curve Cryptography System Design

Descriptions: Elliptic Curve Cryptography implementations are known to be vulnerable to various side-channel attacks and fault injection attacks, and many countermeasures have been proposed. However, selecting and integrating a set of countermeasures targeting multiple attacks into an ECC design is far from trivial. Security, performance and cost need to be considered together. In this project, we propose a generic ECC coprocessor architecture, which is scalable and programmable. We demonstrate the coprocessor architecture with a set of countermeasures to address a collection of side-channel attacks and fault attacks. The programmable design of the coprocessor enables tradeoffs between area, speed, and security.

Related Links:

Elliptic Curve Scalar Multiplication: Attacks vs. Countermeasures by collaboration between Secure Embedded System (SES) group at Virginia Tech and ESAT-COSIC at K.U.Leuven

Presentation Slides for CHES09 Conference

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Last updated on: May 8, 2012

 

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