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Descriptions: In the second phase of the SHA-3 competition, NIST will also pay attention to hardware implementation quality to evaluate the SHA-3 candidates. However, there are still 14 candidates in the running, and evaluating all of them under a consistent hardware platform is a daunting task. We propose a methodology to obtain hardware benchmark results for the candidates, based on two ideas. First, we use high-level synthesis tools to convert C code directly into a hardware description. Second, we use a standard hardware interface for hashing algorithms. Together, these two components define a uniform evaluation mechanism that ensures consistent design methodology, faster than manual hardware design, and that avoids assumptions on the skills of the individual hardware designer. In this contribution, we will discuss the advantages and disadvantages of such a design flow.

Related Links:

C-to-FPGA Using Impulse C by Impulse Accelerated Technologies, Inc.

"Benchmarking of Hardware Implementations of SHA-3 Candidates Using High Level Synthesis", Secure Embedded Systems Lab Technical Report, Mar. 2010. [PDF]

Descriptions: Hardware implementations of block ciphers have been intensively evaluated for years. The traditional hardware profile, including the performance, area and power of a block cipher, only considers the block cipher as a standalone component, and does not consider it as a coprocessor in a system design. In this project we consider system-on-chip (SoC) integration of AES and PRESENT crypto coprocessors, and analyze the system profile in a co-simulation environment and then on an actual FPGA-based SoC platform. Energy, power, performance and implementation results for both the AES- and PRESENT-based systems with the latest FPGA technology and tools are presented. Our research emphasizes the need to consider energy efficiency and performance at system-level when evaluating a block cipher for real embedded systems and SoC designs. After implementing a baseline crypto system with two different bus protocols, Processor Local Bus (PLB) and Fast Simplex Link (FSL), our simulation results reveal that the hardware/software interfaces, as the communication bottleneck, have major impact on the system performance. Experimental results further demonstrate that the PRESENT, a power-efficient light-weight block cipher with lower security level, becomes less energy-efficient than AES when system-integration overhead is included.

Descriptions: Advanced Encryption Standard (AES) has been widely adopted in security suits for wireless sensor networks, which has a considerable impact on the area, power consumption and lifetime of sensors. We find that the S-Box consumes much of the total AES circuit power, and the power dissipation and silicon area can vary more than several-fold, due to different implementation strategies. In this work, a comprehensive study of different standard-cell implementations of the AES S-Box was presented, with respect to silicon area, critical path delay, and average power consumption. By analyzing the power consumption of the AES circuits, we proposed a compact, power-efficient S-Box circuit architecture: a full-balanced Decoder-Switch-Encoder (DSE) architecture. This approach can further reduce the silicon area and power consumption by 14% and 9%, respectively, compared to the original DSE S-Box. Also, our simulation results show that the proposed S-Box is the best choice among nine different S-Box implementations in terms of power-area product, and is optimal for AES crypto design for wireless sensor networks.

Cryptographic substitution boxes (S-boxes) are an integral part of the Advanced Encryption Standard (AES). In this work we conducted a simulation-based correlation power analysis (CPA) attack on AES implementations with different S-box structures. It shows that the abilities of AES and S-boxes to secure against CPA attack are correlated, and an evaluation of the ability of S-boxes to thwart CPA is presented in a quantitative way.

Descriptions: As one of the most important parts in Flat Panel Displayer (FPD ) control ICs, Timing Controllers (TCON) receives and processes signals from frond-end circuits, and then generates control signals to make the LCD panel work correctly. This project follows a standard industry ASIC design flow and FPGA verification with TOP-Down design topology based on the research of FPD display theory and pratical system intergration issues. The final taped out ASIC chip accepts different formats of video signals, and can be applied in systems with various middle-to-small size LCD panels.

Descriptions: Scaler chip is necessary in Flat Panel Display (FPD) systems. It translates the input images, which have different resolution to a fixed resolution image, and then displays on LCD Panels. Based on the research of FPD theory and the system integration issues in FPD systems, this project presents a front-end design of a Scaler chip and FPGA verification with TOP-Down design topology. The scaler chip can process and generate a wide variety of video graphics formats with programmable scaling rations and timing generation, and translate the input video graphics, which have different resolution to the fixed resolution image, and then display clearly and stably pictures on FDP panels. Furthermore, the scaler can be also integrated to other image processing system as an IP core.

Scaling engine is the most important part in Scaler system. This project starts with the research of Scaler system architecture and algorithm, and then a VLSI design of Scaler is implemented. Bilinear Interpolation algorithm and Bicubic Interpolation algorithm are researched and analyzed, and the better one will be selected to reduce chip cost, improve chip frequency and simplify circuit redundancy. The transpose FIR Filter is designed to implement horizontal and vertical scaling module, and pipeline structure is used to improve reliability of data processing and reduce chip cost. The Scaler in Bilinear algorithm can scale image with 0.5-4 ratio, and output with XGA mode. Moreover, due to the limitations of the algorithm, distortion of data signal processing and restriction of display in scaler, the quality of output image becomes worse, so that it is necessary for scaler to add picture enhancement module, including sharpness, contrast, brightness adjustment, gamma correction and dithering.

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Last updated on: May 8, 2012

since Feb. 11, 2008