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Dr. Xu "Eric" Guo [CV]

PhD, Computer Engineering
469 Durham Hall
Virginia Tech
Blacksburg, VA, 24061
USA

Email: xuguo@vt.edu

Note: After graduation from SES@VT in May 2012, I find a new home for my website: https://sites.google.com/site/url2ericguo
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Publications

Copyright Notice: These materials are presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights are retained by authors or by other copyright holders.

 
My up-to-date publication records with citations by Google Scholar: Public Profile URL
Journals
 
 
[J4] M. Srivistav, X. Guo, S. Huang, D. Ganta, M. B. Henry, L. Nazhandali, and P. Schaumont, "Design and Benchmarking of an ASIC with Five SHA-3 Finalist Candidates," Microprocessors and Microsystems: Embedded Hardware Design (MICPRO). (Invited Paper in a Special Issue on "Digital System Security and Safety") (to appear )
[J3] X. Guo and P. Schaumont, "Optimized System-on-Chip Integration of a Programmable ECC Coprocessor," ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol.4, no.1, pp.6:1-6:21, Dec. 2010. (Invited Paper in a Special Issue of ARC'09)[BibTeX]
[PDF]
[J2] J. Xing, X. Zou, and X. Guo, "Ultra-Low Power S-Boxes Architecture for AES," The Journal of China University of Posts and Telecommunications, Vol.15, no.1, Mar. 2008. [BibTeX]
[PDF]

[J1] J. Xiao, X. Zou, Z. Liu, and X. Guo, "A Novel Adaptive Interpolation Algorithm for Image Resizing," International Journal of Innovative Computing, Information and Control, vol.3, no.6(A), pp. 1335-1345, 2007. [BibTeX]

(Before 2007 in Chinese)
 
[J6C] Z. Liu, J. Xiao, X. Zou, and X. Guo, "Edge-based Algorithm of Real-time Image Resizing," Journal of Image and Graphics, vol.13, no.2, 2008.
 
[J5C] Z. Liu, W. Fan, and X. Guo, "HVS-based halftoning schemes for LCD," Journal of Huazhong University of Science & Technology (Nature Science), vol.35, no.4, 2007.
 
[J4C] J. Zhang, Z. Liu, X. Zou, and X. Guo, "Design of Timing Controller for LCD System," Computer and Digital Engineering, vol.35, no.3, 2007.
 
[J3C] J. Xiao, X. Zou, Z. Liu and X. Guo, "The Research of an Adaptive Algorithm for Real-time Image Enhancement," Mircoelectronics & Computer, vol.23, no.5, 2006.
 
[J2C] Z. Liu, X. Guo, X. Zou, and J. Xiao, "Image color enhancement technique based on improved Bayer dithering algorithm," Journal of Huazhong Univ. of Science & Technology (Nature Science), vol.34, no.5, 2006.
 
[J1C] X. Guo, Z. Liu, X. Zou, J. Xiao and H. Zhao, "Picture Sharpness Module Design for Scaler," Computer and Digital Engineering, vol.33, no.5, 2005.
Conferences
 
[PDF]
[C17] X. Guo, M. Srivistav, S. Huang, D. Ganta, M. B. Henry, L. Nazhandali, and P. Schaumont, "ASIC Implementations of Five SHA-3 Finalists," Design, Automation and Test in Europe (DATE2012), March 2012. [BibTeX]
[PDF]
[C16] X. Guo and P. Schaumont, "The Technology Dependence of Lightweight Hash Implementation Cost," ECRYPT Workshop on Lightweight Cryptography (LC2011), November 2011. [BibTeX]
[PDF]
[C15] X. Guo, M. Srivistav, S. Huang, D. Ganta, M. B. Henry, L. Nazhandali, and P. Schaumont, "Pre-silicon Characterization of NIST SHA-3 Final Round Candidates," 14th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2011), August 2011. [BibTeX]
[PDF]
[C14] X. Guo, M. Srivistav, S. Huang, D. Ganta, M. Henry, L. Nazhandali, and P. Schaumont, "Silicon Implementation of SHA-3 Finalists: BLAKE, Grostl, JH, Keccak and Skein," ECRYPT II Hash Workshop 2011, May 2011. [BibTeX]
[PDF]
[C13] Z. Chen, X. Guo, A. Sinha, and P. Schaumont, "Data-Oriented Performance Analysis of SHA-3 Candidates on FPGA Accelerated Computers," Design, Automation and Test in Europe (DATE2011), 2011. [BibTeX]
[PDF]
[C12] X. Guo, S. Huang, L. Nazhandali, and P. Schaumont, "On The Impact of Target Technology in SHA-3 Hardware Benchmark Rankings," Cryptology ePrint Archive, Report 2010/536, 2010. [BibTeX]
[PDF]
[C11] X. Guo, S. Huang, L. Nazhandali, and P. Schaumont, "Fair and Comprehensive Performance Evaluation of 14 Second Round SHA-3 ASIC Implementations," NIST 2nd SHA-3 Candidate Conference, Aug. 2010. [BibTeX]
[PDF]
[C10] J. Fan, X. Guo, E. DeMulder, P. Schaumont, B. Preneel, and I. Verbauwhede, "State-of-the-art of secure ECC implementations: a survey on known side-channel attacks and countermeasures," IEEE International Symposium on Hardware-Oriented Security and Trust (HOST2010) (Embedded Tutorial), Jun. 2010. [BibTeX]
[PDF]
[C9] K. Kobayashi, J. Ikegami, M. Knezevid, X. Guo, S. Matsuo, S. Huang, L. Nazhandali, U. Kocabas, J. Fan, A. Satoh, I. Verbauwhede, K. Sakiyama, and K. Ota, "Prototyping Platform for Performance Evaluation of SHA-3 Candidates," IEEE International Symposium on Hardware-Oriented Security and Trust (HOST2010) , Jun. 2010. [BibTeX]
[PDF]
[C8] X. Guo, J. Fan, P. Schaumont, and I. Verbauwhede, "Programmable and Parallel ECC Coprocessor Architecture: Tradeoffs between Area, Speed and Security," Workshop on Cryptographic Hardware and Embedded Systems (CHES 2009), LNCS5747, pp. 289-303, Sep. 2009. [BibTeX]
[PDF]
[C7] X. Guo and P. Schaumont, "Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA based SoC Platform," 5th International Workshop on Applied Reconfigurable Computing (ARC2009), LNCS5453, pp. 169-180, Springer Verlag, Feb. 2009. [BibTeX]
[PDF]
[C6] X. Guo and P. Schaumont, "Optimizing the HW/SW Boundary of an ECC SoC Design Using Control Hierarchy and Distributed Storage," Design, Automation and Test in Europe (DATE2009), Apr. 2009. [BibTeX]
[PDF]
[C5] Z. Chen, X. Guo, R. Nagesh, A. Reddy, M. Gora, and A. Maiti, "Hardware Trojan Designs on BASYS FPGA Board," Embedded System Challenge Contest in Cyber Security Awareness Week (CSAW08), 2008. (4th Place with Honorable Mention) [BibTeX]
[PDF]

[C4] X. Guo, Z. Chen, and P. Schaumont, "Energy and Performance Evaluation of an FPGA-based SoC Platform with AES and PRESENT Coprocessors," International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2008), LNCS5114, pp. 16-115, Springer Verlag, Jul. 2008. [BibTeX]

[PDF]

[C3] X. Guo, Z. Liu, J. Xing, W. Fan and X. Zou, "Optimized AES Crypto Design for Wireless Sensor Networks with a Balanced S-box Architecture," in Proceedings of International Conference on Informatics and Control Technologies (ICT2006), pp. 203-208, IET, 2006. (Merit Paper Award) [BibTeX]

[PDF]
[C2] Z. Liu, X. Guo, Y. Chen, Y. Han and X. Zou, "On the Ability of AES SBoxes to Secure Against Correlation Power Analysis," in Proceedings of 3rd Information Security Practice and Experience Conference (ISPEC 2007), LNCS 4464,  pp. 43-50, Springer Verlag, 2007. [BibTeX]
[PDF]

[C1] J. Xiao, X. Zou, Z. Liu, and X. Guo, "Adaptive Interpolation Algorithm for Real-time Image Resizing," in Proceedings of International Conference on Innovative Computing, Information and Control (ICICIC'06), vol. 2, pp. 221-224, IEEE, 2006. [BibTeX]

Posters
 
[PDF]
[P7] X. Guo, Meeta Srivistav, S. Huang, Dinesh Ganta, Michael Henry, L. Nazhandali, and P. Schaumont, "Benchmarking ASIC with Five NIST SHA-3 Finalists," Workshop on Cryptographic Hardware and Embedded Systems (CHES 2011) Exhibition Poster, September 2011. [BibTeX]
[PDF]
[P6] X. Guo, Meeta Srivistav, S. Huang, L. Nazhandali, and P. Schaumont, "VLSI Characterization of NIST SHA-3 Finalists," 48th Design Automation Conference (DAC 2011) Work-In-Progress (WIP), June 2011. [BibTeX]
 
[P5] S. Huang, X. Guo, Meeta Srivistav, Dinesh Ganta, L. Nazhandali, and P. Schaumont, "Hardware Evaluation of SHA-3 Candidates," Annual Workshop of Virginia Tech's Center for Embedded Systems for Critical Applications (CESCA), May 2011.
 
[P4] X. Guo, S. Huang, Meeta Srivistav, L. Nazhandali, and P. Schaumont, "The Role of Storage Structures in Lightweight Cryptography," Annual Workshop of Virginia Tech's Center for Embedded Systems for Critical Applications (CESCA), May 2011.
 
[P3] K. Kobayashi, J. Ikegami, M. Knezevid, X. Guo, S. Matsuo, S. Huang, L. Nazhandali, U. Kocabas, J. Fan, A. Satoh, I. Verbauwhede, K. Sakiyama, and K. Ota, "A Prototyping Platform for Performance Evaluation of SHA-3 Candidates," IEEE International Symposium on Hardware-Oriented Security and Trust (HOST2010) , Jun. 2010.
[PDF]
[P2] X. Guo, S. Huang, L. Nazhandali, and P. Schaumont, "Crypto Hardware Benchmark: from SHA-FPGA to SHA-ASIC," Annual Workshop of Virginia Tech's Center for Embedded Systems for Critical Applications (CESCA), May 2010.
[PDF]
[P1] Z. Chen, X. Guo, R. Nagesh, A. Reddy, M. Gora, and A. Maiti, "Hardware Trojan Designs on BASYS FPGA Board," Embedded System Challenge Contest in Cyber Security Awareness Week (CSAW08), 2008. (4th Place with Honorable Mention)

Technical Reports & Tutorials

[PDF]
[T10] X. Guo, "NIST SHA-3 ASIC User Guide," VT CESCA Technical Report, Aug. 2011. [BibTeX]
[PDF]
[T9] X. Guo, "NIST SHA-3 ASIC Datasheet," VT CESCA Technical Report, Aug. 2011. [BibTeX]
 
[T8] X. Guo, "Virginia Tech SHA-3 ASIC Testing Report," VT Secure Embedded Systems Lab Technical Report, June. 2011.
 
[T7] X. Guo, "Preliminary Side-Channel Attack Analysis of 14 2nd round SHA-3 Candidates," VT Secure Embedded Systems Lab Technical Report, Jul. 2010.
[PDF]
[T6] X. Guo, "Tutorial of SHA-3 on SASEBO-GII," ECE 5520 Secure Hardware Design Class Tutorial for Student Final Projects, Mar. 2010.
[PDF]
[T5] X. Guo, "Benchmarking of Hardware Implementations of SHA-3 Candidates Using High Level Synthesis," VT Secure Embedded Systems Lab Technical Report, Mar. 2010. [BibTeX]
 
[T4] X. Guo, "Tutorial of IO-SerDes Implementations on Xilinx ML410 & Altera Stratix-III Development Boards," University of Southern California - Information Sciences Institute Technical Report, Jul. 2009.
 
[T3] X. Guo, "Filter Kernel and Data Generator with IO-SerDes," University of Southern California - Information Sciences Institute Technical Report, Jul. 2009.
 
[T2] X. Guo, "Redsharc Hardware Kernel Generation Using Impulse C," University of Southern California - Information Sciences Institute Technical Report, Aug. 2009.
[PDF]
[T1] X. Guo, M. Gora, "An Instruction Set Extension of theVirtex-5 PowerPC 440 for Elliptic Curve Cryptography," EE5530 Configuration Computing Class Final Project Report, Dec. 2008. [BibTeX]
Presentations
 
[PPT]
"Fair and Comprehensive Performance Evaluation of SHA-3 Hardware Implementations," CESCA Seminar, ECE Department, Virginia Tech, September 2010.
[PPT]
"Optimizing the HW/SW Boundary of a Runtime Programmable and Parallel ECC Coprocessor Design Using Control Hierarchy and Distributed Storage," ESAT-COSIC, K.U.Leuven, Belgium, April 2009.
 
"Area, Delay, and Power Characteristics of Hardware Implementations of the AES S-Box," Research Center for Integrated Circuit Design, Wuhan, China, September 2006.

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Last updated on: May 8, 2012

 

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